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revision 1/february 12, 2001 !"# $%" &

the sk10/100el15w is a low skew 1:4 clock distribution chips designed explicitly for low skew clock distribution applications. this device is fully compatible with mc10el15 & mc100el15. the device can be driven by either a differential or single-ended ecl or, if positive power supplies are used, pecl input signal. if a single-ended input is to be used, the vbb output should be connected to the clk* input and bypassed to vcc via a 0.01 f capacitor. the el15w provides a vbb output for either single-ended use or as a dc bias for ac coupling to the device. the vbb pin should be used only as a bias for el15w as its current sink/source capability is limited. whenever used, the vbb pin should be bypassed to vcc via a 0.01 f capacitor. the el15w features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. when low (or left open and pulled low by the input pull-down resistor) the sel pin will select the differential clock input. the common enable (en*) is synchronous so that the outputs will only be enabled/disabled when they are already in the low state. this avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. the internal flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. ? extended supply voltage range: (vee = ?5.5v to ?3.0v, vcc = 0v) or (vcc = + 3.0v to +5.5v, vee=0v) 50 ps output-to-output skew synchronous enable/disable multiplexed clock input 75k ? internal input pull-down resistors fully compatible with mc10el15 and mc100el15 specified over industrial temperature range: ?40 o c to +85 o c esd protection of >4000v available in 16-pin soic package

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# !" q0 q0* q2 q2* q3 q3* q1 q1* v cc en* clk* v bb sel v ee scl k clk 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 q d 1 0
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revision 1/february 12, 2001

j f r x 45 ? m d c k t 168 pl seating plane 0.25 (0.010) m t b s a s g a p b 8 pl 0.25 (0.010) m b s 16 9 18 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.150 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. 16 pin soic package

+& , - .& & / & 01 , # / &# . # / & & , / #& & / 2& 3 0 / &4 3 0 / & 3 # / 03 4 / 02 3 & / &, 1 & / & 3 # / &. 2 / &2 0 & / &. 0 & / & & 2 / &3 5 / 01 0 & / &. 2 & / & 64 5 / 0 & 3 & / & 7. 0 / &3 5 / &, & & / &. & & / & & 0 / &3 5 / &2 & & / &. & & / & 8& 4 & 4 & , / 3& 5 / 1. 5 5 / &2 2 5 / & "3 5 / && 3 / && 0 & / &. 0 & / &
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revision 1/february 12, 2001 sk10/100el15w dc electrical characteristics (notes 1, 2) 9 : 9 : & 3 0 %& 3 0 & 3 0 & 3 0 %& 3 0 & 3 0 & 3 0 %& 3 0 & 3 0 & 3 0 %& 3 0 & 3 0 + ; + ; < & 0 & & 0 & 5 0 5 3 # 3 # 0 5 0 5 1 # 1 # 0 5 5 5 1 # , # 5 5 2 5 , # 0 2 + +
" ! 3 & 0 & & 0 # 2 / 0 ( , # / 0 ( & # / 0 ( 1 5 / 0 ( , # / 0 ( , # / 0 ( 4 5 / 0 ( 1 5 / 0 ( 3 # / 0 ( , # / 0 ( 3 5 / 0 ( 1 5 / 0 ( 0 # / 0 ( , # / 0 ( . 0 / 0 ( 1 5 / 0 ( ( < & / #3 / 3& / #3 / 3& / #3 / 3& / #3 / 3 (v cc ? v ee = +3.0v to +5.5v ; v out loaded 50 ? to v cc ? 2.0v) ta = ? 40 o c ta = 0 o c ta = +25 o c ta = +85 o c sk10/100el15w ac electrical characteristics * * 9 : $ 9 : $ $ & 1 3 & 4 2 3 1 2 & 3 1 & 0 4 3 , 1 & , 3 & & 3 3 . 2 3 4 1 3 . 1 & & 4 0 . 3 & 0 3 & 0 3 3 . 1 & , 1 3 & 4 & 5 1 3 2 3 1 1 3 & 2 4 3 5 4 3 2 4 < < % % =
> % = & & 5 & 3 & & 5 & 3 & & 5 & 3 & & 5 & 3 ? & 3 0& 3 0& 3 0& 3 0 * ? @ *& & 2& & 2& & 2& & 2 < 8 # & 3 5& & & 0& 3 5& & & 0& 3 5& & & 0& 3 5& & & 0 " 8 " @ 8 2 & & 3 a & & 3 b # / 0 c 3 / 0 c 2 / & ( 2 / & ( # / 0 c 3 / 0 c 2 / & ( 2 / & ( # / 0 c 3 / 0 c 2 / & ( 2 / & ( # / 0 c 3 / 0 c 2 / & ( 2 / & ( ' ? - " ! 9 d & , d & 5 : $ ' $ 3 . 0& 2 #3 & 5& 3 #& 0 5& 1 #3 5 5& , # ta = ? 40 o c ta = 0 o c ta = +25 o c ta = +85 o c (v cc ? v ee = +3.0v to +5.5v ; v out loaded 50 ? to v cc ? 2.0v) &
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revision 1/february 12, 2001 (

! " # $ = 3 0 & 0 ! % 1 0 @ ? = 3 0 & 0 ! % 1 0 @ = 3 0 & & 0 ! % 1 0 @ ? = 3 0 & & 0 ! % 1 0 @ e = 3 0 & 0 e = 3 0 & & 0 notes: 1. 10el circuits are designed to meet the dc specifications shown in the table after thermal equilibrium has been established. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. outputs are terminated through a 50 ? resistor to vcc ? 2.0v. 2. 100k circuits are designed to meet the dc specification shown in the table where transverse airflow greater than 500 lfpm is maintained. 3. minimum input swing for which ac parameters guaranteed. 4. cmr range is referenced to the most positive side of the differential input signal. normal operation is obtained if the high level falls within the specified range and the peak-to-peak voltage lies between vpp (min) and 1v. the lower end of the cmr range varies 1:1 with vee and is equal to vee + 1.3v for vpp < 500 mv and vee + 1.5v for vpp > 500 mv. 5. voltages referenced to vcc = 0v (ecl mode). 6. for standard ecl dc specifications, refer to the ecl logic family standard dc specifications data sheet. 7. for part ordering descriptions, see hpp part ordering information data sheet. division headquarters 10021 willow creek road san diego, ca 92131 phone: (858) 695-1808 fax: (858) 695-2633 marketing group 1111 comstock street santa clara, ca 95054 phone: (408) 566-8776 fax: (408) 727-8994 semtech corporation high-performance products division

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